Senior CMOS IC Layout Engineer

Company: Tbwa Chiat/Day Inc
Location: Torrance
Posted on: January 17, 2025

Job Description:

Red Cell Partners is an incubation firm building and investing in rapidly scalable technology-led companies that are bringing revolutionary advancements to market in three distinct practice areas: healthcare, cyber, and national security. United by a shared sense of duty and deep belief in the power of innovation, Red Cell is developing powerful tools and solutions to address our Nation's most pressing problems.About ClarosClaros innovates at the intersection of power and compute. We build advanced power management solutions that improve AI compute capacity, efficiency and reliability. Claros is an early-stage startup company located in Torrance, CA. If you are looking for challenging work and a strong technical environment with the collaborative & supportive culture, then Claros Tech is the company for you. We offer industry the best competitive pay & benefits and early-stage stock options.Location: Minimum of 3 days a week in the office in Torrance, CA. This is a hybrid position.About the Team:We are open-minded, fast paced, problem solvers that value open dialogue and candor. Our passion is to challenge the status-quo and we embrace transformational thinking. Our response is never "no, but---." instead "yes, if---.". We are mindful of our personal and organizational blinders and try to build an environment where our team members are At Their Best.DescriptionClaros Technologies is seeking a highly skilled, self-motivated Senior Analog IC Layout Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering PMICs (Voltage Regulators, LDO's, DC-DC Buck Converters), ADC/DAC, PLL etc. As a Senior IC Layout Engineer, you'll play a crucial role in translating design concepts into silicon, collaborating closely with circuit designers, and leveraging sophisticated tools.This role will report to the VP of Engineering.Responsibilities:

• Craft layouts for mixed-signal and analog circuits, top-level IC floor planning, chip integration, mask preparation.
• Collaborate with circuit designers to complete the physical layout and verification of high-performance analog/mixed-signal CMOS Integrated Circuits using Cadence Virtuoso XL Layout and PVS Verification tools in cutting-edge process technologies (55nm down to 12nm FinFET).
• Use problem-solving skills, experience, and creativity to layout circuits that meet size, schedule, and performance specifications.
• Interpret LVS, DRC, and ERC reports to find the fastest way to complete the layout, exceeding engineering specifications and expectations. Run physical design verification tools to debug, improve, and verify layout blocks.
• Collaborate with fellow team members on continuous improvement opportunities in the flow, layout techniques, and design methodologies.Required Qualifications:
  • Associates or higher degree with 8+ years of relevant experience in Electronic/IC layout CAD specialization or related program. Demonstrated working Silicon in BCD and advanced CMOS technologies.
  • Experience in the layout of ADCs, DACs, PLLs, LDOs, Bandgaps, Switch caps, DC-DC Buck Converters.
  • Strong understanding of Analog circuit layout fundamentals and best practices including device matching, routing flow and shielding for analog signals, area estimation, power flow, signal flow, and ESD electrical and spacing requirements.
  • Experience in leading the tape-out process and working with the foundry for mask making.
  • Experience creating an IC floor plan for mixed-signal ICs.
  • Knowledgeable with CAD tools like Cadence Virtuoso XL, PVS/Calibre.
  • Experience in providing Bond diagrams for IC packaging.Preferred Qualifications:
    • 2+ years' experience in IC layout design in FinFET technology node.
    • Solid understanding of semiconductor manufacturing process and DFM techniques.
    • Experience with synthesis/advanced place & route tools (Innovus).
    • Experience in IR drop analysis (knowledge in using Cadence tool VOLTUS).
    • Understanding of thermal considerations, latchup, ESD, noise, substrate injection, parasitic extractions, and optimized power routing.
    • Familiar with Cadence Design Environment (CDE) and Unix OS.
    • Programming knowledge in SKILL is a plus.
    • Strong communication skills and a team player.
    • Ability to effectively prioritize and execute tasks in a high-pressure environment.Salary Range: $150,000-$200,000. This represents the typical salary range for this position based on experience, skills, and other factors.#LI-RCPWe're an Equal Opportunity Employer: You'll receive consideration for employment without regard to race, sex, color, religion, sexual orientation, gender identity, national origin, protected veteran status, or on the basis of disability.
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Keywords: Tbwa Chiat/Day Inc, Los Angeles , Senior CMOS IC Layout Engineer, Engineering , Torrance, California